Low Power/High Speed design of a Reed Solomon Decoder

OF T H E PAPER With the spread of Reed Solomon codes t o portable applications, low power RS decoder design has become important. This paper discusses how the Berlekamp Massey Decoding algorithm can be modified in order t o obtain a low power architecture. In addition, modifications thut speed-up the syndrome and error computations are suggested. T h e n the VLSI design of a low power/high speed decoder i s described. T h e power reduction when compared t o the normal design i s estimated.